update

Former-commit-id: bdede6ed1b6f578f2ef046c338caf02d0b29d453 [formerly 7187de361b53e9c8ec121df379b762f2db736ea2]
Former-commit-id: 447d58460fbbfd05ffe08428a1288e392637561d

_embed/public/ace/demo/kitchen-sink/docs/vhdl.vhd

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+library IEEE
+user IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity COUNT16 is
+
+    port (
+        cOut    :out    std_logic_vector(15 downto 0);  -- counter output
+        clkEn   :in     std_logic;                      -- count enable
+        clk     :in     std_logic;                      -- clock input
+        rst     :in     std_logic                       -- reset input
+        );
+        
+end entity;
+
+architecture count_rtl of COUNT16 is
+    signal count :std_logic_vector (15 downto 0);
+    
+begin
+    process (clk, rst) begin
+        
+        if(rst = '1') then
+            count <= (others=>'0');
+        elsif(rising_edge(clk)) then
+            if(clkEn = '1') then
+                count <= count + 1;
+            end if;
+        end if;
+        
+    end process;
+    cOut <= count;
+
+end architecture;
+