update

Former-commit-id: bdede6ed1b6f578f2ef046c338caf02d0b29d453 [formerly 7187de361b53e9c8ec121df379b762f2db736ea2]
Former-commit-id: 447d58460fbbfd05ffe08428a1288e392637561d

_embed/public/ace/demo/kitchen-sink/docs/verilog.v

@@ -0,0 +1,12 @@
+always @(negedge reset or posedge clk) begin
+  if (reset == 0) begin
+    d_out <= 16'h0000;
+    d_out_mem[resetcount] <= d_out;
+    laststoredvalue <= d_out;
+  end else begin
+    d_out <= d_out + 1'b1; 
+  end
+end
+
+always @(bufreadaddr)
+  bufreadval = d_out_mem[bufreadaddr];